1. Field of the Invention
The present invention relates to a method of manufacturing a complementary metal-oxide semiconductor (CMOS). More particularly, the present invention relates to a method of manufacturing a CMOS having an offset spacer structure.
2. Description of the Related Art
Typically, the offset spacer in the MOS manufacturing process is used to lower the overlap capacitance between a gate electrode and a source/drain region, which in turn increases the operation rate of the MOS. A structure called an overlap capacitor is a capacitor constructed by the overlap between the gate electrode of a transistor and the source/drain region. The source/drain region of the transistor is adjacent to and under the gate electrode.
Commonly, the punch-through margins of the channels of the NMOS and the PMOS are reduced as the size of the semiconductor is reduced. Typically, the source/drain region of the PMOS is formed by implanting boron ions into the substrate and the source/drain region of the NMOS is formed by implanting phosphorus ions or arsenic ions into the substrate. Since the radius of the boron ion is relatively small, the thermal diffusion rate of the boron ion in the substrate is relatively fast when an annealing process is performed. The margin of the source/drain region of the PMOS expands more seriously than that of the NMOS after the CMOS is annealed, so that the channel of the PMOS is shorter than that of the NMOS. Therefore, the punch-through problem of the PMOS easily happens and the off current is increased.
Conventionally, the width of the offset spacer of the CMOS is modified to adjust the length of the channels of the PMOS and the NMOS. The punch-through of the PMOS can be greatly improved, however, the saturated current of the drain of the NMOS is decreased, simultaneously. Therefore, the adjustment of the width of the offset spacer has no benefit for the operation rate of the CMOS. Since the channel of the PMOS and the channel of the NMOS cannot be respectively and effectively adjusted, the process window is very narrow. Hence, it is difficult to overcome the off current problem of the PMOS and the problem of the saturated current of the drain of the NMOS, spontaneously.